Method for enhancing the electric connection between a power electronic device and its package

ABSTRACT

An electronic power device of improved structure is fabricated with MOS technology to have a gate finger region and corresponding source regions on either sides of the gate region. This device has a first-level metal layer arranged to independently contact the gate region and source regions, and has a protective passivation layer arranged to cover the gate region. Advantageously, a wettable metal layer, deposited onto the passivation layer and the first-level metal layer, overlies said source regions. In this way, the additional wettable metal layer is made to act as a second-level metal.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention broadly relates to the electric connection of an electronic power device to its package.

[0003] In particular, but not limited to, the invention relates to a device which is fabricated with MOS technology to have at least one gate finger region and source regions on either sides of the gate region, the device also having at least one first-level metal layer arranged to independently contact said gate region and said source regions, and a protective passivation layer on top of the gate region.

[0004] The invention further relates to an advantageous method of electrically bonding the power device to its package. For convenience of explanation, the description below will make reference to discrete power components.

[0005] 2. Description of the Related Art

[0006] As is well known, factors of prime importance in electronic power devices are minimized resistive contributions (Ron) and enhanced heat dissipation from the device when in its conduction mode.

[0007] At present, an assembly technique whereby the bonding wires are replaced with suitably shaped metal strips, or bridging strips, has met both requirements. This technique has proved itself in the instance of bipolar power devices. Also, European Patent No. 0179714 is evidence of a mixed bonding technique, whereby bonding wires are used along with bridging strips as shown in FIG. 1, being known since 1985.

[0008] Recently, an effort has been made to extend the mixed bonding technique to small packages, i.e., packages that enclose small-size integrated circuits, where contacting a pad with a clip would use up an unacceptably large amount of area. As an example, with a 7 mm² device, contacting a gate termination by means of a clip would expend some 0.5 mm², or 7%, of the active area. On the other hand, if a gate termination were contacted by means of a standard-gage bonding wire, the pad bulk would be brought down five times or less, i.e., to occupy less than 1% of the active area.

[0009] For a small-size package, or micro-package, the advantages brought about by the above mixed technique are as tabulated here below: Resistive Contributions Device-to- Distribution of Thermal Assembly Package Current across Resistance to Technique Connection Device Surface Heat Dissipation Standard   2 mΩ 1.5 mΩ 10° C./W Bridge 0.5 mΩ 0.1 mΩ  7° C./W Gain 1.5 mΩ(75%) 1.4 mΩ(93%)  3° C./W (30%)

[0010] However, this mixed bonding technique is subject to certain constraints when used with MOS devices, due to the presence of considerable fingered gate and source metal lines on the device front.

[0011] Bonding fingered structures by means of bridges currently involves breaking the wettable metal line short of the gate fingers, e.g., as shown schematically in FIG. 2.

[0012]FIG. 2 is reproduced from U.S. Pat. No. 6,040,626, which is incorporated by reference herein in its entirety, to show a vertical cross-section taken through a gate finger. The following layers are recognizable: gate metal (19 a), source metal (18), passivation (27), wettable metal (25), conductive adhesive (46), and bridge (30) layers. The lack of wettable metal in the gate finger structure results, especially in structures that are considerable fingered, in a substantial loss of contact area that reflects significantly on the device output resistance (Ron).

[0013] In view of most of the applications on demand today favoring devices with a very low Ron and high speed for high frequency operation, avoidance of conflicting fingered structure requirements and resistive contributions is of primary concern.

BRIEF SUMMARY OF THE INVENTION

[0014] An embodiment of the present invention utilizes a wettable metal line as if it were just a second metal level, and utilizes the first metal level both as a gate metal and a contact layer between the second metal level and the device source.

[0015] In this way, the two metal layers would be separated by a final passivation layer. In addition, breaking the wettable metal line short of the gate fingers would no longer be necessary.

[0016] An embodiment of the invention is directed to a method of fabricating an electronic power device of improved design with MOS technology, which device comprises at least one region of gate fingers and associated source regions on either sides of the gate region, and comprises at least one first-level metal layer, arranged to independently contact said gate region and said source regions, and a protective passivation layer over the gate region, the method including the steps of:

[0017] forming said first metal level over the source regions and the gate fingers;

[0018] forming a passivation layer over the gate fingers to partly overlap the first source metal level; and

[0019] forming a wettable metal layer, on top of the passivation layer and the first-level metal layer, to extend over said source regions.

[0020] An embodiment of the invention further relates to a device as previously indicated and including a wettable metal layer, deposited onto the passivation layer and the first-level metal layer, to extend over said source regions.

[0021] The features and advantages of the invention should become understood from the description of embodiments thereof, given by way of example and not of limitation with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0022]FIG. 1 is a schematic perspective view of an electronic power device where a mixed bonding technique has been used for its interconnection.

[0023]FIG. 2 is a schematic enlarged-scale view in vertical cross-section of an electronic power device having a so-called interconnection gate finger.

[0024]FIG. 3 is a schematic enlarged-scale view in vertical cross-section of an electronic power device of conventional design.

[0025]FIG. 4 is a photograph of a vertical cross-section taken through the power device of FIG. 3 at the gate finger thereof.

[0026]FIG. 5 is a schematic enlarged-scale view in vertical cross-section of an electronic power device formed according to the invention.

[0027]FIG. 6 is a schematic enlarged-scale view in vertical cross-section of a second embodiment of the electronic power device according to this invention.

[0028]FIG. 7 is a schematic enlarged-scale view in vertical cross-section of an electronic power device whose structure includes a plurality of gate fingers.

DETAILED DESCRIPTION OF THE INVENTION

[0029] The applicants have discovered that, areas of the prior art device of FIG. 2 without wettable metal lines that extend beneath the bridge bonding are areas of doubtful adhesion into which solvents from the soft solder may flow. The structure and chemical composition of the adhesive in such areas can be quite different from that in the areas overlying the wettable metal.

[0030]FIG. 3 schematically illustrates the formation of precipitates from said solvents in the area immediately above the passivation layer 27 overlying the gate metal 19 a. The photograph in FIG. 4 shows the cross-section of a prototype formed in conformity with the prior art rules.

[0031] As shown in FIGS. 3-4, the adhesive is a two-part soft solder layer 46, 46′ provided on top of the passivation layer 27 and also on the wettable metal layers 25. However, the solder 46′ over the wettable metal layers 25 has different granulation from the solder 46 that directly covers the passivation layer 27.

[0032] The presence of areas having different chemical compositions may damage the reliability of a product by thermal stressing, especially if fabricated in a wet environment. Thus, the above-described prior technique, related to the bridge bounding when metallization layers are not formed on the finger gate, has at least two major disadvantages:

[0033] 1) a loss of contact area, which may grow to significance in the instance of considerable fingered devices; and

[0034] 2) areas of uncontrolled chemical composition, which may damage reliability.

[0035] An embodiment of this invention provides a method of improving the electric bonding of an electronic power device to its package such that the aforementioned two disadvantages are attenuated and/or obviated.

[0036] With reference to the drawings, in particular to the embodiment shown in FIG. 5, generally shown in schematic form at 1 is an electronic power device whose interconnections have been established in accordance with the inventive method.

[0037] The device 1 is fabricated on a substrate 2 of a semiconductor material to a layout known per se. In other words, the device 1 may be a power device fabricated with MOS technology, which has a gate middle region 3 and respective source regions 4 on either sides of the gate region 3. The drain regions are not shown in FIG. 5, but are positioned on an opposite side of the substrate 2 with respect to the source regions 4.

[0038] The device 1 is a discrete device, and has its gate region 3 formed as a so-called gate “finger”, that is an elongate flat layer whose length dimension exceeds its cross dimension.

[0039] Each region 3, 4 is contacted by a respective metal that can be regarded as a first-level metal. Thus, a gate metal 3′ and respective source metals 4′ are provided.

[0040] As shown best in FIG. 5, a passivation layer 5 separates metal layer 3′ from metal layers 4′.

[0041] Provided on top of each first-level metal layer 3′, 4′ is a covering layer that includes a metal layer 6, 7 which will be wettable in the course of subsequent process steps ending in the finished electronic device.

[0042] The wettable metal layer 6, 7 is formed over the first-level metal layers 3′ and 4′, and on the passivation layer 5, to be substantially flush with the latter.

[0043] A soft solder 9 is provided on top of the wettable metal layer 6, 7 which covers both the source metal layers 4′ and the passivation layer 5. As a result, the solder 46 over the source metal layers 4′ has the same granulation as the solder 46 that is over the passivation layer 5 and gate metal layer 3′.

[0044] The structure of the device is completed with a thin bridge interconnection layer 8 that extends over the solder layer 9.

[0045] Unlike the prior art, the device 1 includes a wettable metal layer 7 that advantageously extends over the passivation layer 5 in continuation of the metal layers 6 that are covering the first-level metals 4′. This layer 7 covers the passivating layer 5 completely.

[0046] In this way, the wettable metal layer 6, 7 is not broken short of the gate fingers, with the benefit of eliminating a non-wettable area that gave way to the formation of precipitates in the prior art.

[0047] Summarized here below are the process steps that form the discrete type of electronic power device 1 having at least two metal levels and a wettable final surface. As an example, the following process steps could be provided:

[0048] a first metal layer, e.g., formed by an aluminum layer 1 to 5 μm thick, suitably doped with impurities such as silicon and/or copper impurities;

[0049] a passivation layer 0.5 to 1 μm thick of deposited oxide;

[0050] a second, wettable metal layer, e.g., formed by a triple layer comprising a stack structure of titanium (˜1000A), nickel (˜3000A), and gold (˜500A) in a stack configuration.

[0051] It should be understood that the layers mentioned above are for exemplification only, it being possible for them to be substituted with any other layers known in the semiconductor industry that exhibit the features specified here below.

[0052] For the first metal level: one or more conductive layers that are compatible for the subsequent steps of forming the passivation layer and second metal level; they are to ensure good contact to the source and gate regions 4 and 3 of device 1.

[0053] For the passivation layer: one or more insulating layers that are compatible for the step of forming the second metal level; the faultiness, integrity and dielectric rigidity of the layers should all be adequate to provide good electrical isolation of the two levels of metal from each other.

[0054] For the second metal level: one or more conductive layers effective to ensure good contact to the first metal layer and provide a solder-wettable surface for use with bridging strips in the mixed bonding method.

[0055] The device 1 uses the wettable metal as a real second metal level, and using the first level as a gate metal and contact layer between the second metal level and the source of the device. The two metal layers are separated by the final passivation layer. In this way, the wettable metal is not broken short of the gate fingers, as illustrated schematically by FIG. 5.

[0056] From a comparison of the embodiment of FIG. 5 with the prior art of FIG. 3, it is evinced that the region overlying the passivation layer of the gate region 3 has now been covered with a wettable metal layer. Accordingly, the area of the gate finger is utilized as a contact area of contact, with the benefit of eliminating the non-wettable area where precipitates had a chance of forming. Furthermore, the double metal levels 3′, 7 provided have the advantage of ensuring a uniform distribution of the current flow even when a number of gate fingers are present, which is highly advantageous from both the rigidity and reliability standpoints.

[0057] This first embodiment of the invention is also uniquely effective in those cases where the final bridge layer 8 is replaced with an IC chip that has to be electrical connected to one or more electrodes of the device underneath. This structure is known in the industry as of “chip-on-chip” and is usually obtained through the use of a conductive adhesive.

[0058] A second embodiment of this invention will now be described with reference to FIG. 6, where co-operating parts structurally and functionally similar to those of the first embodiment shown in FIG. 5 are denoted by the same reference numerals.

[0059] In the second embodiment of this invention, the bridge layer 8 is shaped aligned with the gate fingers to prevent excess pressure on the device layers from causing the passivation layer 5 to crack and create undesired short-circuits across the first 3′, 4′ and second 7 metal levels, notably in those areas where the soft solder is laid quite thinly.

[0060] Briefly, the solder layer 9 is shaped in the source regions 4, laterally of the gate fingers, to enable the bridge layer 8 to reach deeply enough to form sorts of side support legs or feet 10.

[0061] The shaping depth is dependent on the device own inequalities (1 to 4 μm), its width being dependent on the gate finger widths and the position tolerance for the bridge layer 8 on the device 1 (50 to 300 μm).

[0062] Of course, this technique can be applied regardless of whether the wettable metal layer 7 is provided on the gate finger.

[0063] However, the greatest benefit in reliability is to be secured by combining both techniques together, because:

[0064] the wettable metal layer 7 on the gate fingers inhibits the formation of undesired compounds; and

[0065] the shaped bridge layer 8 with side legs or feet 10 resists excess pressure on the structure near the gate fingers.

[0066] For power devices that have considerable fingered areas, the shape of the bridge layer 8 may be an extended one to overlap all the area where the gate finger plurality are present. In this way, the mechanical structure of the bridge layer 8 is made simpler. Briefly, instead of forming supporting feet 10 on either sides of each gate finger, as shown in FIG. 6, much broader (500 to 2000 μm) bridge layers are provided to cover a plurality of gate fingers, as shown schematically in FIG. 7. The example of FIG. 7 may be regarded as an extreme case where the layer 8 covers the whole device 1. Thanks to the supporting feet 20, the mechanical pressure is confined to within the side areas where no fingered structure occurs.

[0067] The device 1 and method described above afford a number of advantages by providing for the introduction of a real second metal level in discrete power devices and, where appropriate, for the bridge layer to be suitably shaped.

[0068] All of the above U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet, are incorporated herein by reference, in their entirety.

[0069] From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims. 

We claim:
 1. A method of fabricating an electronic power device of improved structure with MOS technology, which device includes a gate finger region and corresponding source regions on opposite sides of the gate finger region, a first-level metal layer arranged to independently contact said gate region and said source regions, and a protective passivation layer covering the gate region, the method comprising the steps of: forming said first metal level over the source regions and the gate finger region; forming the passivation layer over the gate finger region in such a manner as to partly overlap the first-level metal layer; and forming a wettable metal layer, on top of the passivation layer and the first-level metal layer placed over said source regions.
 2. A method according to claim 1, wherein said wettable metal layer is covered with a solder layer, in turn covered with a thin bridge bonding layer.
 3. A method according to claim 1, wherein said wettable metal layer is a triple layer comprising a stack structure of titanium, nickel and gold.
 4. A method according to claim 1, wherein said wettable metal layer is covered with a solder layer formed with two reduced regions on the opposite sides of the gate finger region; and a thin bridge bonding layer is deposited onto the solder layer such that supporting feet-shaped side projections from said bonding layer fit in said reduced regions.
 5. An electronic power device fabricated with MOS technology, the power device comprising: a gate finger region; associated source regions positioned at opposite sides of the gate finger region; a first-level metal layer arranged to independently contact said gate finger region and said source regions; a protective passivation layer arranged to cover the gate finger region; and a wettable metal layer deposited onto the passivation layer and the first-level metal layer overlying said source regions.
 6. A device according to claim 5, wherein said additional wettable metal layer provides a second-level metal layer.
 7. A device according to claim 5, wherein said wettable metal layer is coated with a solder layer covered by a thin bridge bonding layer.
 8. A device according to claim 7, wherein said thin bridge bonding layer is shaped to have supporting feet-shaped side projections arranged to reach down to said source regions.
 9. A device according to claim 7, wherein the gate finger region is one of a plurality of gate finger regions occupying a whole area and said thin bridge bonding layer is extended to overlap the whole area occupied by the plurality of gate finger regions, and has peripheral supporting projections arranged to reach down to said source regions on opposite sides of the gate finger regions.
 10. A device according to claim 5, wherein said wettable metal layer is a triple layer comprising a stack structure of titanium, nickel and gold.
 11. A device according to claim 5, wherein said wettable metal layer is coated with a solder layer covered by an integrated circuit chip to provide a chip-on-chip structure.
 12. An electronic power device, comprising: a gate region; associated source regions positioned at opposite sides of the gate region; a protective passivation layer arranged to cover the gate region; an adhesive layer positioned above the passivation layer; and prevention means for preventing chemical reaction of the adhesive layer and the passivation layer.
 13. The device of claim 12 wherein the source regions and the gate region are covered by respective metal contacts and the passivation layer extends between the metal contact of the gate region and the respective metal contacts of the source regions.
 14. The device of claim 13 wherein the prevention means include a wettable metal layer positioned above the gate region and between the passivation layer and the adhesive layer.
 15. A device according to claim 14, wherein the metal contacts of the gate and source regions are part of a first-leval metal layer and the wettable metal layer is part of a second-level metal layer.
 16. The device of claim 12 wherein the prevention means include a wettable metal layer positioned above the gate region and between the passivation layer and the adhesive layer.
 17. The device of claim 16, wherein the wettable metal layer includes a triple layer stack structure of titanium, nickel, and gold.
 18. The device of claim 12, further comprising a thin bridge bonding layer covering the adhesive layer.
 19. The device of claim 18, wherein the thin bridge bonding layer is shaped to have supporting feet-shaped side projections positioned laterally of a central portion of the adhesive layer.
 20. The device of claim 18, wherein the gate region is one of a plurality of gate regions occupying a whole area and the thin bridge bonding layer is extended to overlap the whole area occupied by the plurality of gate regions, and has peripheral supporting projections positioned laterally of a central portion of the adhesive layer. 